library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity jiexi is
	port (
		Arequestrd : in std_logic;
		Brequestrd : in std_logic;
		Crequestrd : in std_logic;
		result     : in std_logic_vector(47 downto 0);
		clock      : in std_logic;
		saddr      : out std_logic_vector(47 downto 0);
		daddr      : out std_logic_vector(47 downto 0);
		length     : out std_logic_vector(15 downto 0);
		pt         : out std_logic_vector(1 downto 0));
end jiexi;

architecture RTL of jiexi is
	signal count  : std_logic_vector(1 downto 0); 
	signal saddrl1: std_logic_vector(31 downto 0);
	signal saddrl2: std_logic_vector(15 downto 0);
	signal daddrl1: std_logic_vector(31 downto 0);
	signal daddrl2: std_logic_vector(15 downto 0);
	signal data   : std_logic_vector(47 downto 0);
	signal req    : std_logic;
	signal lengthl: std_logic_vector(15 downto 0);
	signal en     : std_logic;
begin
	req <= Arequestrd or Brequestrd or Crequestrd;
	process(Arequestrd, Brequestrd, Crequestrd, clock)
	begin 
		if (clock'event and clock = '1') then
			data <= result;
			if (req = '0') then
				count <= "00";
			else
				if (count = "00") then
					en <= '0';
					count <= count + 1;
					if (Arequestrd = '1') then
						pt <= "00";
					end if;
					if (Brequestrd = '1') then
						pt <= "01";
					end if;
					if (Crequestrd = '1') then
						pt <= "10";
					end if;
				elsif (count = "01") then
					daddrl1 <= data(31 downto 0);
					count <= count + 1;
				elsif (count = "10") then
					daddrl2 <= data(47 downto 32);
					saddrl1 <= data(31 downto 0);
					count <= count + 1;
				elsif (count = "11") then 
					if (en = '0') then
						saddrl2 <= data(47 downto 32);
						lengthl <= data(31 downto 16);
						en <= '1';
					end if;
				end if;
			end if;
			if (en = '1') then
				saddr <= saddrl1 & saddrl2;
				daddr <= daddrl1 & daddrl2;
				length<= lengthl;
			else
				saddr <= (others => '0');
				daddr <= (others => '0');
				length<= (others => '0');
			end if;
		end if;
 	end process;
end RTL;